1. Field of the Invention
The present invention relates to a ferroelectric memory which stores data in correspondence with the polarization state of a ferroelectric substance and, more particularly, to a column select circuit which selectively transfers data from a sense amplifier to a data line.
2. Description of the Related Art
A ferroelectric memory is read-accessed by transferring data from a memory cell to a bit line and amplifying the data, as in a DRAM. FIG. 1 is a circuit diagram showing main part associated with such read operation of a ferroelectric memory. A memory cell MC having a cell transistor CT and ferroelectric capacitor FC and a dummy cell DMC formed from a transistor DCT are connected to a pair of bit lines BL and /BL. The cell transistor CT and transistor DCT are N-channel MOS transistors (NMOS transistors). One end of the current path of the cell transistor CT is connected to the bit line BL. The other end is connected to one electrode of the ferroelectric capacitor FC. The gate is connected to a word line WL. The other electrode of the ferroelectric capacitor FC is connected to a plate line PL. One end of the current path of the transistor DCT is connected to the bit line /BL. The other end is connected to a reference voltage source VREF. The gate is connected to a dummy word line DWL.
The current paths of bit line precharge NMOS transistors Q1 and Q2 are connected between the bit lines BL and /BL and a ground point VSS. A bit line precharge signal BLPRE is supplied to the gates of the NMOS transistors Q1 and Q2.
A sense amplifier SA which amplifies and holds the data of the memory cell MC is connected between the bit lines BL and /BL. The sense amplifier SA comprises NMOS transistors Q3 to Q5 and P-channel MOS transistors (PMOS transistors) Q6 to Q8. The operation of the sense amplifier SA is controlled by sense amplifier enable signals SEN and /SEP. The current paths of the NMOS transistors Q3 and Q4 are connected in series between the bit lines BL and /BL. The current path of the NMOS transistor Q5 is connected between the ground point VSS and the connection point of the current paths of the NMOS transistors Q3 and Q4. The sense amplifier enable signal SEN is supplied to the gate of the NMOS transistor Q5 to ON/OFF-control the NMOS transistor Q5. The current paths of the PMOS transistors Q6 and Q7 are connected in series between the bit lines BL and /BL. The current path of the PMOS transistor Q8 is connected between a power supply VDD and the connection point of the current paths of the PMOS transistors Q6 and Q7. The sense amplifier enable signal /SEP is supplied to the gate of the PMOS transistor Q8 to ON/OFF-control the PMOS transistor Q8. The gates of the NMOS transistors Q3 and Q4 are connected to the connection point between the current paths of the PMOS transistors Q6 and Q7. The gates of the PMOS transistors Q6 and Q7 are connected to the connection point between the current paths of the NMOS transistors Q3 and Q4.
The current path of an NMOS transistor Q9 is connected between the bit line BL and a data line DQ. The current path of an NMOS transistor Q10 is connected between the bit line /BL and a data line /DQ. The NMOS transistors Q9 and Q10 function as a column select gate. A column select signal CS is supplied to the gates of the NMOS transistors Q9 and Q10.
The current paths of PMOS transistors Q11 and Q12 are connected in series between the data lines DQ and /DQ. The power supply VDD is connected to the connection point between the current paths of the PMOS transistors Q11 and Q12. A data line precharge signal /DQPRE is supplied to the gates of the PMOS transistors Q11 and Q12.
Output of data read out from the memory cell MC or input of data to be written in the memory cell MC is done by an I/O circuit IOC connected to the data lines DQ and /DQ.
Capacitors C1 and C2 indicated by broken lines are the parasitic capacitances of the data lines DQ and /DQ.
FIG. 2 is a timing chart showing the operation waveforms of the circuit portion shown in FIG. 1. First, the bit line precharge signal BLPRE is set to high level (“H” level) to turn on the NMOS transistors Q1 and Q2, thereby setting the bit lines BL and /BL in a low level (“L” level) state (timing tA). The operation of setting the bit lines BL and /BL to “L” level as initial settling will be referred to as precharge for the descriptive convenience.
Next, the word line WL and plate line PL are raised from “L” level to “H” level (timing tB) to apply a voltage to the ferroelectric capacitor (memory cell capacitor) FC, thereby transferring data corresponding to the polarization state of the ferroelectric film in the memory cell capacitor FC to the bit line BL. When “1” data is stored in the memory cell capacitor FC, polarization reversal occurs at PA=VAA and BL=0 V in read operation, and charges are transferred to the bit line BL. To the contrary, when “0” data is stored, no polarization reversal takes place, and therefore, no charges are transferred to the bit line BL.
Simultaneously with the read operation from the memory cell MC, the dummy word line DWL changes to “H” level, so the reference potential from the reference voltage source VREF is applied to the bit line (reference bit line) /BL that is complementary to the bit line BL. Accordingly, the potential of the bit line /BL is set to an intermediate potential between the potential obtained when “1” data is read out and that obtained when “0” data is read out.
When the sense amplifier enable signal SEN changes to “H” level and /SEP to “L” level to activate the sense amplifier SA (timing tC), the potential difference between the bit line BL and the reference bit line /BL is amplified and held. As a result, when “1” data is read out from the memory cell MC, the potential of the bit line BL changes to VAA, and the potential of the reference bit line /BL changes to 0 V. On the other hand, when “0” data is read out, the potential of the bit line BL changes to 0 V, and the potential of the reference bit line /BL changes to VAA.
When “0” data is read out to the bit line BL, a voltage −VAA is applied to the memory cell capacitor FC, and the “0” data is restored to the memory cell capacitor FC because the potential of the bit line BL is 0 V, and the potential of the plate line PL is VAA (timing tD). On the other hand, when “1” data is read out to the bit line BL, and the potential of the plate line PL changes to 0 V later, a voltage +VAA is applied to the memory cell capacitor FC, and the “1” data is restored because PL=0 V and BL=VAA (timing tF).
The data amplified and held by the sense amplifier SA is transferred to the data lines DQ and /DQ when the column select signal CS is activated (timing tE) to turn on the NMOS transistors Q9 and Q10. Accordingly, data corresponding to the potentials of the data lines DQ and /DQ is output from the I/O circuit IOC.
As described above, when the column select gate is constituted by only the NMOS transistors Q9 and Q10, and the data lines DQ and /DQ are precharged to “H” level, the data latched by the sense amplifier SA is not destroyed normally even when both the data lines DQ and /DQ are connected to the power supply (potential VAA) (this state equals an infinite parasitic capacitance). This is because the threshold voltage of the NMOS transistors Q9 and Q10 has a finite magnitude, and the “0” data latched by the sense amplifier SA by the potential VAA of the data lines DQ and /DQ cannot be completely raised to the VAA level. That is, when the data line DQ or /DQ and the bit line BL or reference bit line /BL are at level near the potential VAA, data destruction is prevented using a characteristic that the data lines and bit lines are not completely rendered conductive.
However, since the data line DQ that is precharged to “H” level is connected to the bit line BL through the column select gate formed from the NMOS transistor Q9, only the “L”-level side potential, i.e., the 0 V potential of the potentials of the bit lines BL and /BL, which are amplified by the sense amplifier SA, i.e., becomes higher by ΔV.
At this time, as shown in FIG. 3, since the potential of the plate line PL is VAA, and the potential of the bit line BL is VSS(0 V)+ΔV, the voltage applied to the memory cell capacitor FC is −(VAA−ΔV) that is lower than −VAA, i.e., the ideal write voltage for “0” data.
To apply the ideal write voltage −VAA to the memory cell MC, the potential of the plate line PL is changed to 0 V after the column select signal CS is set in an inactive state, and the potential of the bit line BL returns to 0 V again. In this case, however, the performance is poor because the time until the potential of the bit line BL returns from ΔV to 0 V is added to the cycle time of the ferroelectric memory.
To avoid the above-described problem, a structure in which a column select gate is formed as a CMOS transfer gate, i.e., the current paths of an NMOS transistor and a PMOS transistor are connected in parallel has been proposed (e.g., Jpn. Pat. Appln. KOKAI Publication No. H08-273372).
In this structure, since the current drivability of the column select gate increases, the transfer speed for data latched by the sense amplifier SA to the data lines DQ and /DQ is high. This structure is therefore suitable for a high-speed memory.
However, since the number of elements and the number of control signal lines increase, the layout area and the power consumption of the control circuit become large. In addition, since a PMOS transistor and an NMOS transistor are combined, they are always rendered conductive regardless of the combination of potentials of the bit lines BL and /BL and data lines DQ and /DQ. Since no dead zone is present, operation is unstable. For this reason, unless the parasitic capacitances C1 and C2 of the data lines DQ and /DQ are much smaller than the capacitances of the bit lines BL and /BL, data latched by the bit lines BL and /BL may be destroyed by the initial potential of the data lines DQ and /DQ. Hence, the data lines DQ and /DQ cannot be shared by a number of sense amplifiers SA. This increases the layout area and results in difficulty in applying the structure to a large-capacity memory.
As described above, in the conventional ferroelectric memory, when data read out from a memory cell is restored, the data degrades, and no data read margin can be ensured.
In addition, if this problem should be solved, the number of elements and the number of control signal lines increase. For this reason, the layout area and the power consumption of the control circuit also become large.